Strained-Silicon Transistors (CMOS)

Strained-Si CMOS is on the roadmaps of every major CMOS manufacturer. At Cambridge we developed a number of CMOS processes and strained-Si devices. The major reason is that the circuit performance can be substantially increased by increasing the mobility of the electrons and holes in CMOS transistors.

On the left are the IV characteristics from a 0.25 µm CMOS process run as part of the U.K. HMOS programme. The reduction of the current at high voltages is related to self-heating effects as the Si0.8Ge0.2 virtual substrate has a 20 times lower thermal conductivity than Si.

A cross sectional TEM image of a typical virtual substrate with strained-Si cap grown for the U.K. HMOS programme.

The subthreshold slopes are reasonable for wafers processed in a university cleanroom. As the wafers were processed with a fully thermal budget including a 1050 ˚C implant activation for 30 s, Ge diffusion is an issue.

The most impressive work here was the hole mobilities achieved using LEPECVD virtual substrates from Hans von Känel with Warick solid source MBE strained-Si cap layers. For Si0.8Ge0.2 virtual substrates, the hole mobilities are some of the highest published.

The electron mobilities produced in these devices were not as high as many others in the literature

Significant publications:

S. Olsen, L. Driscoll, K. Kwa, S. Chattopadhyay, A. O'Neill, A. Waite, Y. Tang, A. Evans, D.J. Norris, A.G. Cullis, D.J. Paul and D.J. Robbins "High performance strained Si/SiGe nMOSFETs using a novel CMOS architecture" IEEE Transactions on Electron Devices 50(9), pp1961-1969 (2003)

S.H. Olsen, A.G. O'Neill, S. Chattopadhyay, L.S. Driscoll, K.S.K. Kwa, D.J. Norris, A.G. Cullis and D.J. Paul, "Study of single and dual-channel designs for high performance strained-Si/SiGe n-MOSFETs" IEEE Transactions of Electron Devices, 51(7), pp1245-1253 (2004)

D.J. Paul, M. Temple, S.H. Olsen, A.G. O'Neill, Y.T. Tang, A.M. Waite, C. Cerrina, A.G. R. Evans, X. Li, J. Zhang, D.J. Norris and A.G. Cullis, "Strained-Si n-MOS surface channel and buried Si0.7Ge0.3 compressively strained p-MOS fabricated in a 0.25 µm heterostructure CMOS process" Materials Science in Semiconductor Processing 8(1-3), pp343-346 (2005)